Getting a first pass SoC (System on chip) in today’s semiconductor world is a herculean task.  The design complexity of the SoC ( in terms of millions of gates), the speed of operation( in GHz) and the Software complexity ( multiple IP’s working in unison) only seem to be headed North, while the Physical gate length(technology node-nm), Power Consumption( Operation voltage) and the development Time( Design to production cycle) seem to be going only South. Industry study shows that more than 50% SOC’s are re-spun/re-designed with each spin costing few millions of Dollars.

Challenges:  System on Chip (SoC) is So Challenging given

• Multiple IP’s need to be plugged in and made to work in unison in a SoC
• Need to find and fix bugs earlier in the design cycle as the cost for fixing a bug increases exponentially as the design cycle progresses
• Complex end-uses cases need to be verified on the SoC within a limited time period
• Reduce time to market and enable product development with a SoC+ Verified Software

Validation Approach:

While there is no thumb rule or formulated methodology to reduce time to market a SoC, the focus is to reduce the time in every phase of the entire design cycle. The trend is to ensure re-usability of IP’s and SOC architecture even if it is from your own competitor.

The traditional methodologies like Software Simulation, Hardware Accelerated simulation (usually FPGA’s), Formal/Semi formal verification are effective but have limitations as well.

• Directed Tests aimed at Module/IP level and do not focus on an end user application
• Sequential execution- Software development starts only after first Silicon sample is available
• Chances of discovering  critical bugs in use-case scenario is high on Silicon

Practical and preferred Approach:

Hardware Emulation is the preferred and practical approach. This enables

• Running of close to real-world software applications on emulated hardware
• Finding out Hardware/Software inter-dependencies much early in the cycle thereby reducing rework
• Application testing in Pre-silicon environment and provides early start for Post-Si related development activities

Palladium from Cadence, Veloce from Mentor Graphics, and Zebu from Eve are HW emulation solutions accepted industry wide

HwApps team from Sasken has worked with leading North American Tier1 Semiconductor company on validating 35+ SoC’s  ( ranging from single core ~2M gates  --10+ cores ~50M gates) using the hardware emulation approach.  The success rate has been phenomenal

• 70% of the SOC’s functionality has been validated on Day 1 of silicon arrival
• Screening time for the Silicon samples has been reduced to few minutes
• Fully validated Silicon samples have reached early customers within the first week of Silicon sample arrival
• Less than 5% of the SOC’s had be re-spun due to critical/killer bug getting into the silicon

With increasing complexity of SOC’s, reducing time to market and the need to bring out first pass silicon most of the semiconductor companies involved in SOC’s design/manufacture are taking the hardware emulation approach.